This invention relates generally to automatic test equipment and more specifically to low cost automatic test equipment for semiconductor devices.
Semiconductor devices, such as memory chips and micro controllers, are usually tested at least once during their manufacture. Testing is conventionally performed with automated equipment called a xe2x80x9ctester.xe2x80x9d A tester is a computer controlled device with many input/output points. Each of the input/output points is connected to one lead of the semiconductor device through a device called a prober or a handler.
So that one tester can be used to test many different types of semiconductor devices, the tester can be programmed to generate xe2x80x9cpatterns.xe2x80x9d The pattern defines what stimuli are applied to the device under test and the expected responses to that stimuli. Defective devices are detected because they do not produce the expected responses.
To make a tester which is the most useful, it is desired that the tester be able to apply or check for any value at any time at any pin of the device being tested. Typically, a pattern is made up of a string of vectors. Each vector contains information about the values to be applied to or expected to be detected at each pin of the device under test during one period of the tester""s operation. This information includes the data value, timing information and format information.
Format information indicates at a minimum whether the data is a value which should be driven or is a value expected to be observed at the pin. In some testers, format information also indicates the format which a valid logic 1 or 0 should take. Examples of formats are return-to-zero, nonreturn-to-zero and surround by complement.
Most testers allow the length of a period to be programmed. The period is generally the same for signals applied to all pins in the tester. The timing information is programmed as a delay relative to the start of the period.
To provide the required flexibility, a typical tester has an architecture with some centralized control, or xe2x80x9cglobal,xe2x80x9d control circuitry. In addition, there are multiple identical circuits called xe2x80x9cchannel electronicsxe2x80x9d or more simply xe2x80x9cchannels.xe2x80x9d Each channel provides the signals for one pin of the device under test.
FIG. 1 shows a typical prior art tester 100. A test pattern is stored in memory 120. For each cycle of tester operation, test system control 110 reads one vector from memory 120. Then, the data, format and timing information are provided to a plurality of channels 114. In addition, test system control 110 provides a timing signal to each of the channels which defines a reference time from which all delays are calculated. This is sometimes called the xe2x80x9cbeginning of periodxe2x80x9d signal or xe2x80x9cperiod clockxe2x80x9d.
Each channel 114 contains several timing generators 114. Each timing generator produces a timing signal, sometimes called an xe2x80x9cedge,xe2x80x9d a programmed time after the beginning of period signal. There are multiple timing generators 116 because each is dedicated to perform a specific function. For example, one timing generator is dedicated to turning on the drive voltage and one is dedicated to turning off the drive voltage. Another is dedicated to starting a comparison operation while another to stopping the comparison operation.
The edges from all of the timing generators 116 are passed to formatter 118. Formatters 118 contain the drivers and comparators which actually provide or measure the data. The time when each operates is controlled by the edge signals. In this way, signals are driven to or measured at the device under test 112.
For a tester which can test even a modestly complicated part, there will be more than fifty and likely more than one hundred channels 114. The channel circuitry, thus, accounts for a large portion of the cost of tester 100. The cost can be particularly high because low cost technologies, such as CMOS, are not suitable for the channel circuitry in many testers. Rather, ECL components are widely used because they can operate at high clock rates and are very stable.
CMOS circuitry made using widely available 0.8 micron processes has a maximum operating frequency of approximately 100 MHz. Components made with state of the art 0.3 micron processes can extend the operating frequency to as much as 200 MHz. This means that the clock likely has a resolution of only 10 nsec, and in the best case a resolution of 5 nsec. When CMOS digital signals are synchronized relative to the clock, they have a resolution of only 5 to 10 nsec. Often, a resolution less than 250 psec resolution is required for a tester. Further, programmed values should be very accurate.
To provide finer resolution, the delay is broken into two pieces: the integer number of clock periods plus some fractional portion of a clock signal. A counter produces an output pulse after the required integer number of clock periods. The fractional part of the delay is provided by delaying this pulse in either a programmable delay line or analog circuitry called a timing xe2x80x9cinterpolatorxe2x80x9d or xe2x80x9cvernier.xe2x80x9d Timing generation circuitry of this type is described in U.S. Pat. No. 4,231,104 to St. Clair and U.S. Pat. No. 5,274,796 to Conner.
The difficulty with using CMOS for such an arrangement is that the delay of CMOS circuits varies as a function of temperature of the devices. The delay of a CMOS circuit changes approximately 0.3%/xc2x0 C. to 0.4%/xc2x0 C. Such a large change as a function temperature means that the same delay programmed into a channel will produce different results when operated at different temperatures. In addition, CMOS components have large part-to-part variations. Delays through parts which have been identically processed can vary by as much as 20 or 30%.
One simple approach is to calibrate the tester each time the operating temperature changes significantly. Many calibration techniques are known. U.S. Pat. No. 4,724,378 to Murray et al. describes an external calibration device used to compute timing correction values which are stored in the tester memory. Other techniques are known for deriving the calibration values, including the addition of circuitry to the tester to derive the calibration values. However, the process of calibrating the tester can be very time consuming.
Mechanical solutions to keep the CMOS chips at uniform temperatures are possible. However, requiring cooling components is expensive and defeats the purpose of using CMOS to provide a low cost tester. It also does not eliminate the delay differences caused by part-to-part variations.
An alternative way to compensate for differential delays is to heat the CMOS chips. U.S. Pat. No. 4,980,586 to Sullivan et al, uses circuitry on the chip to heat the CMOS chip to the desired operating temperature. In addition, that patent describes a feed back mechanism in which a ring oscillator on the chip is used as part of circuit to measure actual delays. The frequency of the signal in the ring oscillator is inversely proportional to the delay. A control signal is derived from the frequency of oscillation in the ring oscillator and then used to adjust the amount of heat generated by the heating circuit.
While such an approach can compensate for temperature as well as part-to-part variation, it requires that the CMOS chip run at an elevated temperature. Operation in this condition can lead to reliability problems and also requires greater power consumption.
A similar solution is described in U.S. Pat. Nos. 4,902,986 and 5,345,186. In each of these patents, the ring oscillator is incorporated into a phased locked loop in which the frequency produced by the ring oscillator is compared to a stable reference frequency to produce a feedback signal. The feedback signal controls the supply voltages of the components in the ring oscillator. As the supply voltage is varied, the delay through the loop changes. In this way, the frequency of the signal in the ring oscillator is synchronized to the stable reference frequency. As a result, the delay through the delay chain is constant. The same supply voltage is used to provide power to other devices in time critical paths on the chip.
This technique eliminates the disadvantage of operating the CMOS part at an elevated temperature. However, it has the added disadvantage of requiring that different parts of the CMOS chip be connected to different supply voltages. Such an arrangement can be difficult to design and fabricate.
A very similar compensation technique is described in U.S. Pat. No. 4,641,048 to Pollock. However, that patent is not specifically limited to CMOS circuitry. Thus, that patent generally shows the control signal fed to a bias input of the components rather than being the supply voltage.
Also, the need to compensate for delay variations in CMOS components has been long known. Examples of various techniques are found in U.S. Pat. No. 3,970,875 to Leehan, U.S. Pat. No. 3,996,481 to Chu et al., U.S. Pat. No. 4,008,406 to Kawagoe, U.S. Pat. No. 4,346,343 to Berndlmaier et al., U.S. Pat. No. 4,473,762 to Iwahahi et al., U.S. Pat. No. 4,494,021 to Bell et al. and U.S. Pat. No. 4,514,647 to Shoji.
Each of these techniques can aid in making a precise and accurate CMOS tester. However, we have recognized that these techniques still yield testers which often have less than the desired accuracy in programming edges. In particular, we have recognized that these techniques are primarily useful in adjusting for variations in ambient temperature. They can not compensate well for the fact that the operating temperature of CMOS components changes as a function of operating frequency.
We have recognized that temperature changes due to changes in operating frequency pose a particular problem in the channel circuitry of a CMOS tester. In particular, a tester usually operates in a xe2x80x9cburst mode.xe2x80x9d When a device to be tested is first connected to the tester, the channel circuitry is not generating signals. It is essentially operating at zero frequency and is generating very little heat. When a device is tested, the signals in the channel circuitry are being generated at a high frequency, typically 50 MHz to 100 MHz. However, a test of one device lasts only a matter of seconds. During that test or xe2x80x9cburst,xe2x80x9d the CMOS parts in the tester heat up, resulting in a change in timing accuracy. After the burst, the CMOS parts start to cool down. Thus, during the entire burst, the temperature of the parts in the tester is changing.
Another reason that temperature of the CMOS parts changes during a burst is that signals of different frequencies might be required at different parts of the burst in order to fully test the device under test. To allow these types of tests, commercially available testers allow timing values to be changed xe2x80x9con the fly,xe2x80x9d which means that the timing values are changed during a burst. Thus, the same timing generator might be programmed to generate edges with a period of 50 nsec during the first half of the burst but then be changed to generate edges with a period of 100 nsec at a different part of the burst. These edge rates represent signals of different frequency and the circuitry, such as formatter 118, would, if made of CMOS, operate at varying frequencies during the burst and thus with varying delays.
Traditional calibration techniques can not address the problem of temperature transients during a burst because they can not be run during a burst. Using a resistive heater controlled in response to a differential delay is not fully effective at addressing this problem. There is a lag between the time when heat generated by the CMOS part changes and the time when the effect of changing the resistance heater is observed. This lag is caused in part by the time it takes for heat generated in the CMOS circuitry to change the temperature of the ring oscillator. The lag is also caused in part by the time it takes for the change in heat generated by the resistive heater to influence the temperature of the CMOS components in the channel circuitry.
There is also a lag when compensation is provided by controlling the supply voltage of elements in the ring oscillator. Though the change in delay is faster than when a heater is used, some time is still required for the heat generated by the CMOS channel circuitry to influence the delay in the ring oscillator.
We have recognized that improved timing accuracy of a CMOS tester could be provided if delays in channel circuitry could be controlled in response to changes in operating frequency with a very fast time constant.
With the foregoing background in mind, it is an object of the invention to provide a CMOS tester with improved timing accuracy.
It is also an object to provide a CMOS tester with temperature compensation in proportion to the operating frequency in the channel circuitry.
It is also an object to provide a CMOS tester with temperature compensation in each timing path in the channel circuits which is responsive to the frequency of the signals in the channel circuit.
It is also an object to reduce the number of CMOS parts which are subject to signals of varying frequencies in channel circuits of a tester.
The foregoing and other objects are achieved in a CMOS tester having a plurality of channel circuits, each having several timing paths. A frequency controlled delay compensator is included in a portion of the timing paths. As the frequency of the timing signals change and therefore change the temperature in the timing path, the delay compensators adjust the delay in the path and therefore compensate for changes in delay due to temperature.
In a preferred embodiment, the frequency controlled delay compensators are resistive heaters which are cycled on and off. The on cycle time, and hence the amount of heat generated, varies inversely with the frequency of the signal in the timing path.
According to one embodiment, the resistive heaters are selectively located near high power dissipation areas on a chip, such as output pads.
In other embodiments, the resistive heaters are additionally or alternatively selectively located near circuitry which processes signals having a programmable frequency.
According to another feature of the invention, programmable delays in each timing path are generated by breaking the programmed delay into an integer and fractional number of clock pulses. Each clock pulse is delayed by the fractional amount. The integer number of clock pulses are counted separately. The count of the integer number of clock pulses enables a circuit which passes the next clock pulse delayed by the fractional amount. In this way, the frequency of the signals in the circuitry providing the fractional delays is uniform in all channels during a programmed burst.